1. Field of the Invention
The present invention is custom operations for use in processor systems which perform functions including multimedia functions, such as, for example, a system with an ability to handle high-quality video and audio and for performing specialized, high-function operations.
2. Description of the Related Art
A system may include a general-purpose CPU and additional units to serve as a multi-function PC enhancement vehicle. Typically, a PC must deal with multi-standard video and audio streams, and users desire both decompression and compression, if possible. While the CPU chips used in PCS are becoming capable of low-resolution real-time video decompression, high-quality video decompression and compression are still not possible. Further, users demand that their systems provide live video and audio without sacrificing responsiveness of the system.
For both general-purpose and embedded microprocessor-based applications, programming in a high-level language is desirable. To effectively support optimizing compilers and a simple programming model, certain microprocessor architecture features are needed, such as a large, linear address space, general-purpose registers, and register-to-register operations that directly support manipulation of linear address pointers. A recently common choice in microprocessor architectures is 32-bit linear addresses, 32-bit registers, and 32-bit integer operations although 64 and 128 bit systems are currently in development.
For data manipulation in many algorithms, however, data operations using the entire number of bits (i.e., 32 bits for a 32-bit system) are wasteful of expensive silicon resources. Important multimedia applications, such as decompression of MPEG video streams, spend significant amounts of execution time dealing with eight-bit data items. Using 32-, 64-, 128-, . . . , bit operations to manipulate small data items makes inefficient use of 32-, 64-, 128-, . . . , bit execution hardware in the implementation. Therefore, custom operations may operate on data items simultaneously and thus, improve performance by a significant factor with only a tiny increase in implementation costs.
Although a similar performance increase through other means may be achieved, e.g., executing a higher number of traditional microprocessor instructions per cycle--these other means are generally prohibitively expensive for low-cost target applications. Additionally, use of m-bit operations, for example 32-bit operations, to manipulate small data items of n-bits where n&lt;m is an inefficient use of m-bit execution hardware in the implementation.